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Dual RF LDMOS Bias Controllers
with I 2 C/SPI Interface
CAPACITIVE DAC
ADCIN_
CONTROL LOGIC
AGND
TRACK MODE
CAPACITIVE DAC
ADCIN_
CONTROL LOGIC
AGND
Figure 4. Equivalent ADC Input Circuit
HOLD/CONVERSION MODE
Analog Input Track and Hold
The equivalent circuit (Figure 4) shows the
MAX1385/MAX1386 ADC input architecture. In track
mode, a positive input capacitor is connected to
ADCIN_ and a negative input capacitor is connected to
AGND. After the T/H enters hold mode, the difference
between the sampled positive and negative input volt-
ages is converted. The input capacitance charging rate
determines the time required for the T/H to acquire an
input signal. If the input signal’s source impedance is
high, the required acquisition time lengthens.
Any source impedance below 300 ? does not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by lengthen-
ing t ACQ or by placing a 1μF capacitor between the
positive input and AGND. The combination of the ana-
log input source impedance and the capacitance at the
analog input creates an RC filter that limits the analog-
input bandwidth.
Analog-Input Bandwidth
The ADC’s input-tracking circuitry has a 10MHz band-
width to digitize high-speed transient events. Anti-alias
prefiltering of the input signals is necessary to avoid
high-frequency signals aliasing into the frequency band
of interest.
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